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25XX080A/B
2.5
Read Status Register Instruction
The Write Enable Latch (WEL) bit indicates the status
( RDSR )
The Read Status Register instruction ( RDSR ) provides
access to the Status Register. The Status Register may
be read at any time, even during a write cycle. The
Status Register is formatted as follows:
of the write enable latch and is read only. When set to
a ‘ 1 ’, the latch allows writes to the array or the Status
Register, when set to a ‘ 0 ’, the latch prohibits writes to
the array or the Status Register. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the Status
Register. These commands are shown in Figure 2-4
TABLE 2-2:
STATUS REGISTER
and Figure 2-5.
7 6 5 4 3 2 1
W/R – – – W/R W/R R
WPEN X X X BP1 BP0 WEL
0
R
WIP
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is in Figure 2-7. These bits are nonvolatile and are
W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the
25XX080A/B is busy with a write operation. When set
to a ‘ 1 ’, a write is in progress, when set to a ‘ 0 ’, no write
is in progress. This bit is read-only.
shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
FIGURE 2-6:
CS
READ STATUS REGISTER TIMING SEQUENCE ( RDSR )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
instruction
SI
0
0
0
0
0
1
0
1
high-impedance
data from Status Register
SO
7
6
5
4
3
2
1
0
DS21808D-page 10
? 2007 Microchip Technology Inc.
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